1/6 april 2002 AN1424 application note configuring fpgas with flash+psd contents n fpga configuration basics C xilinx specific C typical implementation C psd solution n summary n references there are several well-documented methods for configuring field programmable gate arrays (fpgas). each method in- volves transferring configuration data from some sort of non- volatile memory (nvm) to the fpga. there are usually many modes for doing the transfer, including stand alone (master mode), or in conjunction with an embedded microcontroller (peripheral or slave mode). the method chosen depends on many factors specific to the particular application, such as: n speed of configuration n number of i/o pins available n microcontroller configuration n simplicity of design n multiple configuration files n board space n cost. invariably, cost is usually the main factor for determining the method chosen. easy flash ? psd8xxf devices are members of a family of flash memory-based peripherals for use with embedded sys- tems. these programmable system devices (psds) consist of memory, logic, and i/o. when coupled with a low-cost micro- controller (mcu), the psd forms a complete embedded flash memory system that is 100% in-system programmable (isp). this application note shows the benefits of using a psd8xxf to provide the necessary functions for configuring an fpga. the psd8xxf devices are not only extremely low cost com- pared to other solutions, but also provide all of the inherent benefits associated with flash-based psds, such as: n in-system programmable and (re)configurable n additional memory (flash, optional sram, and optional secondary flash memory or eeprom) n low power consumption n integration of many parts, including memory, programmable logic, decode logic, and security n flexibility n improved reliability n reduced number of components n board space savings
AN1424 - application note 2/6 n reduced development time. fpga configuration basics each manufacturer of fpgas has their own unique configuration format. usually, the configuration is made up of an internal data structure containing preamble bits, length count, data frame size, and so on. the configuration is normally generated by the manufacturers development software. although this note focuses specifically on the xilinx families of fpgas, the general concepts presented are applicable to all configurable fpgas. xilinx specific there are at least six different programming modes available, which are user selectable via three mode pins on the fpga: m0, m1, and m2. the programming modes include: C mode 0master serial C mode 1master parallel (address = 0000 up) C mode 2slave parallel (express modexc4000ex and xc5200 families only) C mode 3master parallel (address =ffff down) C mode 4reserved C mode 5peripheral parallel C mode 6reserved C mode 7slave serial for a complete description of these modes, refer to xilinxs data sheets. typical implementation a typical application using an 8031 microcontroller connected to an external 128 kbyte flash, an octal latch, and an fpga configured in slave serial mode, is shown in figure 1. both the program code and the fpga configuration code are stored in the flash. this is the simplest method for configuring the fpga since the mcu simply bit-bangs data into it. figure 1. typical implementation for fpga configuration in slave serial mode vcc vcc vcc reset ad0 ad2 ad4 ad6 ad7 ad5 ad3 ad1 a8 a9 a10 a11 a12 a13 a14 a15 a0 a1 a2 a3 a4 a5 a6 a7 d7 d6 d5 d4 d3 d2 d1 d0 s1 u5a 7414 1 2 u2 74als373 3 4 7 8 13 14 17 18 1 11 2 5 6 9 12 15 16 19 d0 d1 d2 d3 d4 d5 d6 d7 oc g q0 q1 q2 q3 q4 q5 q6 q7 u4 xc3xxx reset m2 m1 m0 cclk din init done/prog~ u3 29f010 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 13 14 15 17 18 19 20 21 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 ce oe we dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u1 80c31 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 ea/vp x1 x2 reset int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd wr psen ale/p txd rxd 16 mhz ai06684
3/6 AN1424 - application note psd solution although the solution above is simple, the flash memory cannot be programmed or updated after it is sol- dered to the pc board. using a low cost psd8xxf device provides the optimal solution for configurable fpga applications. the psd8xxf contains the needed memory to store the system program code, the fpga program code, and the fpga configuration data. the memory of the psd can be programmed/ updated over the jtag channel at any time. figure 2 shows one example of how a psd8xxf might in- terface to an fpga configured in slave serial mode. figure 2. fpga configuration circuit using a psd8xxf chip selects for internal components and external devices are generated by the psds decode pld (dpld). the address demultiplexing latch shown in figure 1 (u2) is absorbed by the programmable mcu interface of the psd. the psd also replaces the two microcontroller ports lost when accessing external memory, which can be used for general purpose i/o or to provide the control signals needed to interface to the fpga. since the psd provides plenty of memory, it could be used to store multiple configurations for the fpga. these configurations could be changed (re-programmed) in-system when necessary using the jtag port. the flexibility of the psd8xxf i/o ports allow them to be configured for many functions, including: n standard i/o n chip select outputs n latched address outputs n additional address inputs n registered i/o. the circuit designer now has the freedom to select whichever fpga mode is best suited to the particular application. another option for the designer would be to use peripheral mode or express mode. in this case, one of the psd8xxf ports would be configured as an 8-bit parallel data port. some of the other port pins could then be used to provide any additional control signals necessary for that particular mode. also note that the output micro ? cells can be connected to form a loadable shift register that could be used to load fpgas in parallel. see application note 55 for more information on cpld usage. ai06685 vcc vcc reset ad2 ad1 ad0 ad3 ad4 ad5 ad6 a8 a9 a10 a11 a13 a14 a15 ad7 a12 tdo tdi tck tms /rd ale /wr /psen /reset s1 u5a 7414 1 2 u4 xc3xxx reset m2 m1 m0 cclk din init done/prog~ u2 psd813f5 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 46 20 19 18 17 14 13 12 11 50 47 49 48 8 9 10 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 adio15 (tms) - pc0 (tck) - pc1 (vstby) - pc2 (tstat) - pc3 (terr) - pc4 (tdi) - pc5 (tdo) - pc6 pc7 cntl1 cntl0 cntl2 reset pd2 pd1 pd0 u1 80c31 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 ea/vp x1 x2 reset int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd wr psen ale/p txd rxd u5b 7414 3 4 16 mhz jtag header
AN1424 - application note 4/6 summary the psd8xxf family is an ideal solution for embedded control applications that use configurable fpgas because multiple configurations can be stored in the psd and updated as necessary using the jtag port. also, with the psd, you have four multi-purpose ports that can be used in conjunction with the mcu, fp- ga, and other external devices to form a complete solution. references for more information on the psd8xxf family and its uses, visit our web site at www.st.com/psm and the following documents: n psd813f family data sheet n application note an1153 jtag informationpsd8xxf for detailed use of the jtag channel n application note an1171cpld primerpsd8xxf for details on the cpld and i/o pins n application note an1154psd813f1/80c31 design tutorial for details on psd i/o, gpld, logic simulation, and psdsoft features.
5/6 AN1424 - application note table 1. document revision history date rev. description of revision sep-1999 1.0 document written (an065) in the wsi format 03-jan-2002 1.1 front page, and back two pages, in st format, added to the pdf file references to waferscale, wsi and psdsoft 2000 updated to st, st and psdsoft express 12-apr-2002 1.2 document converted to st format
AN1424 - application note 6/6 for current information on psd products, please consult our pages on the world wide web: www.st.com/psm if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.psd@st.com (for application support) ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states.
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